1. Field of the Invention
The present invention generally relates to a substrate and a method for manufacturing the same and, more particularly, a substrate having a penetrating via penetrating a base member, wiring connected to the penetrating via, and a method for manufacturing the same.
2. Description of the Related Art
In these years, by using fine processing technology of a semiconductor, packages called MEMS (Micro Electro Mechanical Systems) for micro machines and substrates such as interposers mounting a semiconductor device therein, are developed. The above described substrate includes wirings formed on both sides of the substrate and penetrating vias penetrating the substrate and electrically connecting the wirings formed on both sides of the substrate.
FIG. 1 is a diagram showing a conventional substrate. As shown in FIG. 1, a substrate 10 is composed of a silicon member 11, an insulating layer 13, penetrating vias 15, wirings 17, solder resists 19 and 24, and wirings 21. In the silicon member 11, through-holes 12 are formed. The insulating layer 13 is formed on the surface of the silicon member 11 wherein a through-hole 12 is formed. The insulating layer 13 is provided for insulating the silicon member 11 from the penetrating via 15, the wiring 17, and the wiring 21. The penetrating via 15 which is cylindrical in shape is provided in the through-hole 12 where the insulating layer 13 is formed. Moreover, an edge part 15a of the penetrating via 15 and a surface 13a of the insulating layer 13 are to be even, and another edge part 15b of the penetrating via 15 and another surface 13b of the insulating layer 13 are to be even. The above described penetrating via 15 is formed by the steps of forming a seed layer by a spattering method on the silicon member 11 where the insulating layer 13 is formed, and separating out a conductive metal layer such as Cu on the seed layer by the electrolytic plating method and growing the metal layer (See Patent Document 1, for example).
The wiring 17 having an external connection terminal 18 is provided on the upper surface of the silicon member 11 so as to be connected to the edge part 15a of the penetrating via 15. MEMS and a semiconductor device 25 are mounted on the external connection terminal 18. Solder resist 19 exposing the external connection terminal 18 is provided on the upper surface of the silicon member 11 so as to cover the wiring 17 except the external connection terminal 18.
The wiring 21 having an external connection terminal 22 is provided on the undersurface of the silicon member 11 so as to be connected to the other edge part 15b of the penetrating via 15. The external connection terminal 22 is provided for being connected to another substrate such as a motherboard. Solder resist 24 exposing the external connection terminal 22 is provided on the undersurface of the silicon member 11 so as to cover the wiring 21 except the external connection terminal 22.
[Patent Document 1] Japanese Patent Application Laid-Open Disclosure No. 1-258457
The shape of the conventional penetrating via 15 is cylindrical. However, water infiltrates into a gap between the edge part 15a of the penetrating via 15 and the insulating layer 13, and a gap between the other edge part 15b and the insulating layer 13, and thereby, the penetrating via 15 becomes degraded and the electrical connection reliability of the penetrating via 15 connecting the wirings 17 and 21 is also degraded. Moreover, according to the conventional method for forming the penetrating via 15, the separated conductive metal layer on the surface of the seed layer is formed on the inside edges of the through-hole 12 and the conductive metal layer is grown along the inside edges of the through-hole 12, and thus, a void (cavity) forms near the center of the penetrating via 15. Therefore, the electrical connection reliability of the penetrating via 15 connected to the wirings 17 and 21 is degraded.